1. Field of the Invention
The invention relates generally to a semiconductor structure and method of manufacturing and more particularly to an on-chip PIN diode working at millimeter wave range and a method of manufacturing the same using a dual epitaxial process.
2. Background Description
High frequency applications such as, millimeter wave devices (f30 GHz), require multifunction circuits with different types of devices for optimum operation. For example, in advanced microwave devices, transmitter circuits of communication and radar systems use heterojunction bipolar transistors (HBTs). But, in this same device, receiver circuits comprise III-V material based field effect transistors (FETs), such as high electron mobility transistors (HEMTs), to minimize the noise figure and therefore improve the receiver sensitivity. The performance of such multifunction circuit devices can be reduced if all of the subsystem functions can be accomplished with the use of a common device process technique to integrate all of the relevant advanced devices onto the same substrate.
In currently known manufacturing processes, high-speed three terminal devices and microwave diodes such as PIN diodes, etc. are fabricated by epitaxial growth techniques on high resistive or insulating substrates. In one conventional process, conventional on-chip PIN diodes are processed by sharing the NPN C-B structures. However, this poses problems with the overall performance of the device. For example, known processing using a single wafer technology cannot provided a thin film collector for a high performance NPN (bipolar) device and a thick film collector for high breakdown voltage devices.
By way of one specific example, it is known to implant an HBT subcollector region of a first conductivity in a substrate at a first surface. A PIN diode region of a first conductivity is then implanted in the substrate at the first surface and spaced from the HBT subcollector region. Next, an HBT base/PIN diode layer of a second conductivity is selectively grown on the i-layer over the HBT subcollector region and the PIN diode region. Then, an HBT emitter layer on the first conductivity is selectively grown over the HBT base/PIN diode layer. An isolation region is then made by polysilicon filled deep trench and shallow trench at the boundary between the HBT subcollector region and the PIN diode region, with the deep trench isolation region extending into the substrate. Next, the HBT emitter layer is etched away over the PIN diode region, and conductive contacts are formed to the HBT emitter layer, HBT base layer, HBT subcollector region, PIN diode anode region and PIN diode cathode region. Thus, in a single process, HBTs and PIN diodes can be fabricated on the same substrate.
It is the aim of the above technique to use a common i-layer between the devices and to use modified processing techniques to enable the growth of all structures on the same wafer without compromising the performance of any of the devices. Although the process described above contemplates fabricating each circuit on a single substrate (i.e., eliminating the need to use separate substrates and then connecting the substrates in a module), there still remain several limitations. To name one, for example, the PIN diodes i-layer cannot be freely tuned to achieve desired T/R switch speed due to NPN performance requirements.